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While the hardware has a typical microcontroller architecture, with several pins dedicated to I/O, the instruction set is typical of a minicomputer and resembles that of the PDP-11

In around 1982 Signetics released the N8X305, the successor to the 8X300. It was functionally compatible but increased the general purpose registers to 13 from 8 among some other instruction improvements that greatly improved upon the data handling deficiencies of the 8X300. Processor speed was also boosted to 10MHz. (200ns instruction time vs 250ns for the 8X300) The N8X305 also used the same pin-out as the 8X300 and the same 50pin DIP package (as well as adding a 68pin PLCC).

In 1980 Philips Semiconductor asked a small local computer company (Instrument Design Agency) to design, manufacture, and market a PLC20 development system based on the 2650 microprocessor. This system contained two 8 inch floppy disk units and a 2650 computer system in a eurocard format rack. The software consisted of a disk operating system, text editor, PLC20 assembler and a utility to upload the generated binary code. This system was sold all over Europe to industries that were using the PLC20

The 2650 was supplied in a 40 pin plastic or ceramic DIL enclosure. An external single phase clock signal and a single 5V supply were needed.

The 2650 was designed to be easy to interface: a complete microcomputer required only a few standard external components, rather than a specific 'chipset'. To this end, all inputs and outputs were TTL compatible, and the control signals were designed to make interfacing to standard components simple - a minimal computer system (an intelligent typewriter controller^[1]) required only 5 standard TTL I.C.'s beside the 2650 itself.

The 2650 had many unusual features when compared to other microprocessors of the time:

• It was a fully static NMOS 8-bit microprocessor. The static nature was unusual for the time, and meant that the processor could be halted simply by stopping the clock signal. Programmers made grateful use of this feature to "single step' through a program using a push-button switch to generate the clock pulses.
• Unique was the 8-level 15-bit wide stack for the subroutine and interrupt return addresses which was integrated into the processor. The stack pointer used 3 bits of the upper status register. This meant subroutines and interrupts could only be nested 8 levels deep.
• The processor had only 13 real address lines, a further 2 address lines were connected to a 2-bit 'page register', resulting in a 32 kb address space. The page register was set when an absolute (direct) branch instruction-which used a full 15-bit address, was executed. All logical and arithmetic instructions used a 13-bit address augmented by the contents of the page register, thereby limiting their scope to an 8 kb page. These 2 upper address lines were also used (multiplexed) to select the appropriate I/O port during I/O operations (Control port, Data port or Extended port).

• Although the 2650 had only one interrupt input, this was a 'vectored' interrupt-the interrupting device needed to put a zero-relative displacement on the data bus, that would be used as the operand of a ZBSR (zero branch to subroutine relative) instruction to branch to the specified interrupt routine. Therefore, using indirect addressing, a maximum of 30 interrupt vectors could be stored in the first 64 bytes of memory. (The first three bytes were needed to hold an unconditional branch to the 'reset' routine). Theoretically, negative displacements could be used to access interrupt routines in the last page of memory.

This vectored interrupt is also reminiscent of the PDP-11 minicomputer

• Also unusual were the two status registers, which could be set, tested and cleared under program control.

Besides the 3-bit stack pointer,the upper status register also contained:

• Interrupt inhibit bit
• Flag bit that drives the FLAG output pin
• Sense bit that follows the state of the SENSE input pin.
• Bits 3 and 4 unused in the 2650A, and user programmable in the 2650B

The lower status register contained the following bits:

• CC0 and CC1. Condition code bits that reflect the contents of a register (zero, positive or negative), or the result of a compare instruction.
• IDC. Intermediate Carry
• RS. Select register bank A or B
• WC. With or without Carry
• 0. Overflow
• COM. Logical or Arithmetic Compare - If arithmetic compare is chosen, the MSB of the data is considered to be a SIGN-bit.
• Carry.

Of the 7 8-bit general purpose registers, register R0 was always available, the other 6 registers were divided into 2 banks of 3, and the bank could be switched by setting or clearing the 'Bank Select' bit in the lower status register.

Apple II computers Category:Early microcomputers