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18:3718:37, 15 June 2024 diff hist +114‎ Zilog Z80 ‎ Undid revision My mistake: Was reading the wrong manual. current Tag: Undo
18:3318:33, 15 June 2024 diff hist −114‎ Zilog Z80 ‎ →‎Derivatives: the eZ80 does not have LEA nor PEA instructions Tag: Reverted
18:1318:13, 15 June 2024 diff hist +61‎ Zilog Z80 ‎ →‎Example code: note: LDIR does not fully save AF. H, P/V, and N are reset.
15:2615:26, 15 June 2024 diff hist +96‎ Zilog eZ80 ‎ Register infobox: Although eZ80 manual (UM007715-0415) shows I as 8-bit in ADL register diagram on page 13, I is actually 16-bit to support LD I,HL and LD HL,I instructions and type 2 ADL interrupts as described in manual. current

23:3823:38, 14 June 2024 diff hist +94‎ Zilog eZ80 ‎ →‎Design: Register infobox: Push AF pushes an extra byte of zeros.
21:2321:23, 14 June 2024 diff hist +360‎ Talk:Zilog eZ80 ‎ →‎24bit?: Reply current Tag: Reply
16:4116:41, 14 June 2024 diff hist +6,265‎ Zilog eZ80 ‎ Added ADL mode register infobox
16:3816:38, 14 June 2024 diff hist +4,009‎ User:RastaKins/sandbox ‎No edit summary current

14:5614:56, 11 June 2024 diff hist 0‎ National Semiconductor PACE ‎ →‎INS8900: 8208 was a tranceiver. 8212 was a latch. current
12:2412:24, 11 June 2024 diff hist −22‎ Motorola 68000 ‎ →‎Moving to 16-bit: The IMP-16 was not a multi-chip module. It was packaged in several 24-pin DIPs.
04:2204:22, 11 June 2024 diff hist −6‎ MOS Technology 6502 ‎ →‎Registers: singular, MOS:OVERLINK

15:4615:46, 10 June 2024 diff hist +322‎ Talk:Intel 8086 ‎ →‎compact encoding inspired by 8-bit processors: Reply current Tag: Reply
15:1915:19, 10 June 2024 diff hist +2‎ TRSDOS ‎ →‎Example code: align object and source blocks current
00:5800:58, 10 June 2024 diff hist +8‎ Zilog Z80 ‎ Removed lower price claim. The Z80 was about double the price of the 8080A. See "Z-80 price" discussion in talk archive 1 page.

23:4723:47, 30 May 2024 diff hist −5‎ Orthogonal instruction set ‎ →‎Basic concepts: binary not hexadecimal current
23:3223:32, 30 May 2024 diff hist +28‎ Zilog Z80 ‎ →‎New syntax: Change orthogonalization link to point to a computer link rather than a vector math link.

04:2704:27, 29 May 2024 diff hist 0‎ Zilog Z80 ‎ 8080 8-bit registers are A, B, C, D, E, H, L

19:4119:41, 24 May 2024 diff hist +39‎ Intel 8086 ‎ →‎The first x86 design: Programmers use shifts for powers of two and shift/adds/subs for small multipliers but I believe it is impossible to write a general 16 x 16 bit multiply on the 8086 that is faster than the MUL instruction.

23:1823:18, 22 May 2024 diff hist +15‎ Upper memory area ‎ →‎See also: Added A20 current
15:4415:44, 22 May 2024 diff hist +33‎ Template:Sidebar arithmetic logic circuits/ALUComponentsSidebar ‎ Added XOR bitwise operation current
15:0415:04, 22 May 2024 diff hist +2‎ PDP-11 architecture ‎ →‎See also: forgot the bullet current
15:0315:03, 22 May 2024 diff hist +55‎ PDP-11 architecture ‎ Added "See also"
14:0014:00, 22 May 2024 diff hist +6‎ Data General Nova ‎ Moved the picture of the mutt-ly 840 with a 1220 front panel down to the front panel section which desperately needs a picture. current

17:3717:37, 21 May 2024 diff hist +31‎ Slow jam ‎ →‎See also: a republic inspired by slow jam current