Memory buffer register

A memory buffer register (MBR) or memory data register (MDR) is the register in a computer's CPU that stores the data being transferred to and from the immediate access storage. It was first implemented in von Neumann model. It contains a copy of the value in the memory location specified by the memory address register. It acts as a buffer,^[1] allowing the processor and memory units to act independently without being affected by minor differences in operation. A data item will be copied to the MBR ready for use at the next clock cycle, when it can be either used by the processor for reading or writing, or stored in main memory after being written.

This register holds the contents of the memory which are to be transferred from memory to other components or vice versa. A word to be stored must be transferred to the MBR, from where it goes to the specific memory location, and the arithmetic data to be processed in the ALU first goes to MBR and then to accumulated register, and then it is processed in the ALU.

The MDR is a two-way register.^[2] When data is fetched from memory and placed into the MDR, it is written to go in one direction. When there is a write instruction, the data to be written is placed into the MDR from another CPU register, which then puts the data into memory.

The memory data register is half of a minimal interface between a microprogram and computer storage; the other half is a memory address register (MAR).

During the read/write phase, the Control Unit generates control signals that direct the memory controller to fetch or store data.

References

^ #Mett, Percy (1990), Mett, Percy (ed.), "Hardware", Introduction to Computing, London: Macmillan Education UK, pp. 117–162, doi:10.1007/978-1-349-08039-7_5, ISBN 978-1-349-08039-7, retrieved 2024-01-15
^ Dharshana, K.S; Balasubramanian, Kannan; Arun, M. (2016). Encrypted computation on a one instruction set architecture. pp. 1–6. doi:10.1109/ICCPCT.2016.7530376. ISBN 978-1-5090-1277-0. Retrieved 2024-01-15.

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[1] #Mett, Percy (1990), Mett, Percy (ed.), "Hardware", Introduction to Computing, London: Macmillan Education UK, pp. 117–162, doi:10.1007/978-1-349-08039-7_5, ISBN 978-1-349-08039-7, retrieved 2024-01-15

[2] Dharshana, K.S; Balasubramanian, Kannan; Arun, M. (2016). Encrypted computation on a one instruction set architecture. pp. 1–6. doi:10.1109/ICCPCT.2016.7530376. ISBN 978-1-5090-1277-0. Retrieved 2024-01-15.

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